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19-1963; Rev 0; 2/01
ILABLE N KIT AVA EVALUATIO
16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs
General Description
The MAX3891 serializer converts 16-bit wide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. The MAX3891 is ideal for interfacing with high-speed digital circuitry. This device accepts single-ended LVPECL data inputs and delivers differential LVPECL data and clock outputs. An internal 2.5Gbps serial clock, synthesized by a fully integrated PLL that accepts multiple input reference clock rates, retimes the output data stream. The MAX3891 operates from a single +3.3V supply and accepts differential LVPECL reference clock rates of 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz. A CML loopback data output is provided to facilitate system diagnostic testing. The MAX3891 is available in the extended temperature range (-40C to +85C) in a 64-pin TQFP exposed pad (EP) package. o Single +3.3V Supply o 495mW Power Consumption o Exceeds ANSI, ITU, and Bellcore Specifications o 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion o Clock Synthesis for 2.5Gbps o Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) o Additional High-Speed Output for System Loopback Testing o Single-Ended PECL Data Inputs o Differential PECL Clock Inputs and Serial Data Outputs
Features
MAX3891
________________________Applications
2.5Gbps SDH/SONET Transmission Systems 2.5Gbps Access Nodes Add/Drop Multiplexers Digital Cross-Connects ATM Backplanes
Ordering Information
PART MAX3891ECB TEMP. RANGE -40C to +85C PIN-PACKAGE 64 TQFP EP*
*EP = Exposed Pad
Pin Configuration
TOP VIEW
PCLKO+ PCLKOCLKSET RCLK+ RCLKPDIO PDI1 GND GND
48 GND 47 VCC 46 PDI2 45 VCC 44 PDI3 43 VCC 42 PDI4 41 VCC 40 PDI5 39 VCC 38 PDI6 37 VCC 36 PDI7 35 VCC 34 PDI8 33 GND
FIL+
FIL-
VCC
VCC
VCC
VCC PDI10
64
63 62 61 60 59 58
57 56 55 54 53 52 51 50 49
GND VCC SLBOSLBO+ VCC SOS VCC SCLKOSCLKO+
1 2 3 4 5 6 7 8 9
MAX3891
VCC 10 SDO- 11 SDO+ 12 VCC 13 VCC 14 PCLKI+ 15 PCLKI- 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PDI14
VCC
PDI13
PDI12
PDI15
PDI11
PDI9
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TQFP
Typical Application Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
VCC
16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC ..................................................................-0.5V to +5.0V All Inputs, FIL+, FIL- .............................-0.5V to (VCC + 0.5V) Output Currents PECL Outputs (SDO, SCLKO, PCLKO) ..................50mA CML Outputs (SLBO)...................................................15mA Continuous Power Dissipation (TA = +85C) 64-Pin TQFP-EP (derate 45.5mW/C above +85C) ........2.9W Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 1% to (VCC - 2V), CML loads = 50 1% to VCC, TA = -40C to +85C. Typical values are at VCC = +3.3V and TA = +25C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP 150 VCC - 1.025 VCC - 1.085 VCC - 1.81 VCC - 1.83 VCC - 1.16 VCC - 1.81 -10 -10 -60 -60 CLKSET = GND or VCC 2.0 0.8 -10 -10 +10 +10 MAX 230 VCC - 0.88 VCC - 0.88 VCC - 1.62 VCC - 1.555 VCC - 0.88 VCC - 1.48 +10 +10 +60 +60 500 UNITS mA
Supply Current ICC PECL outputs unterminated, SOS = iow PECL OUTPUTS (SDO, SCLKO, PCLKO) TA = 0C to +85C Output Voltage High VOH TA = -40C TA = 0C to +85C Output Voltage Low VOL TA = -40C PECL INPUTS (PDI_, PCLKI, RCLK) Input High Voltage Input Low Voltage Input Current High PDI_, RCLKI Input Current Low PDI_, RCLKI Input Current High PCLKI Input Current Low PCLKI PROGRAMMING INPUT (CLKSET) CLKSET Input Current TTL INPUT (SOS) TTL Input High Voltage TTL Input Low Voltage TTL Input High Current VIH VIL IIH ICLKSET VIH VIL IIH IIL IIH IIL
V
V
V V A A A A A V V A A
TTL Input Low Current IIL CURRENT MODE LOGIC (CML) OUTPUTS (SLBO) CML Differential Output Voltage Swing CML Single-Ended Output Impedance VOD RO RL = 50 to VCC
100 50
400
mV
2
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16:1 Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, PECL loads = 50 1% to (VCC - 2V), CML loads = 50 1% to VCC, TA = -40C to +85C. Typical values are at TA = +25C and VCC = +3.3V, unless otherwise noted.) (Note 1)
PARAMETER Serial Clock Rate Parallel Data Setup Time Parallel Data-Hold Time PCLKO to PCLKI Skew Output Jitter Generation (SCLKO) PECL Differential Output (SDO, SCLKO) Rise/Fall Time Parallel Input Clock Rate Reference Clock Input (RCLK) Rise/Fall Time Parallel Clock Output (PCLKO) Rise/Fall Time Serial-Clock Output (SCLKO) to Serial-Data Output (SDO) Delay tR, tF fPCLKI tR, tF tR, tF 20% to 80%, f = 155.52MHz 20% to 80% SYMBOL fSCLK tSU tH tSKEW (Notes 2, 3) (Notes 2, 3) Figure 1 Jitter bandwidth = 12kHz to 20MHz 20% to 80% 155.52 1.0 1.0 300 700 0 +4.0 3 120 CONDITIONS MIN TYP 2.488 MAX UNITS GHz ps ps ns psRMS ps MHz ns ns
MAX3891
tSCLK-SD
SCLKO rising edge to SDO edge
110
290
ps
Note 1: AC characteristics are guaranteed by design and characterization. Note 2: Setup and hold times are relative to the rising edge of PCLKI+, measured by applying a 155.52MHz differential parallel clock with rise/fall time = 1ns (20% to 80%). See Figure 1. Note 3: Setup and hold time measurements assume that the PCLKI and PDI signals are from the same source and have identical common-mode voltages, swings, and slew rates.
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX3891 toc01
SERIAL-DATA OUTPUT EYE DIAGRAM
MAX3891 toc02
SERIAL-DATA OUTPUT JITTER
MAX3891 toc03
200
fRCLK = 155.52MHz
180 SUPPLY CURRENT (mA)
160
140
120 PECL OUTPUTS UNTERMINATED 100 -50 -25 0 25 50 75 100 100ps/div TEMPERATURE (C) 5000ps/div TOTAL WIDEBAND RMS JITTER = 2.059ps, PEAK-TO-PEAK JITTER = 16.70ps
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3
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
Pin Description
PIN 1, 17, 33, 48, 49, 63 2, 5, 7, 10, 13, 14, 19, 21, 23, 25, 27, 29, 31, 32, 35, 37, 39, 41, 43, 45, 47, 51, 53, 56, 60, 64 3 4 6 8 9 11 12 15 16 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 54 55 57 58 NAME GND Ground FUNCTION
VCC
+3.3V Supply Voltage
SLBOSLBO+ SOS SCLKOSCLKO+ SDOSDO+ PCLKI+ PCLKI-
System Loopback Negative Output. Enabled when SOS is high. System Loopback Positive Output. Enabled when SOS is high. System Loopback Output Select, TTL Input. System loopback disabled when low. Negative PECL Serial Clock Output Positive PECL Serial Clock Output Negative PECL Serial Data Output Positive PECL Serial Data Output Positive PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal. Negative PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs. Note that data is updated on the positive transition of the PCLKI signal.
PDI15 to PDI0
Single-Ended PECL Parallel Data Inputs. Data is clocked on the PCLKI positive transition. PDI15 is transmitted first.
PCLKO+ PCLKORCLK+ RCLK-
Positive PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Negative PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead management circuit. Positive Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. Negative Reference Clock Input. Connect a PECL-compatible crystal reference clock to the RCLK inputs. Reference Clock Rate Programming Pin: CLKSET = VCC: Reference Clock Rate = 155.52MHz CLKSET = Open: Reference Clock Rate = 77.76MHz CLKSET = 20k to GND: Reference Clock Rate = 51.84MHz CLKSET = GND: Reference Clock Rate = 38.88MHz Filter Capacitor Input. Connect a 0.33F capacitor between FIL+ and FILFilter Capacitor Input. Connect a 0.33F capacitor between FIL+ and FILGround. This must be soldered to a circuit board for proper electrical and thermal performance (see exposed pad package information).
59
CLKSET
61 62 EP
FILFIL+ Exposed Pad
4
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16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
PCLKO
tSKEW PCLKI
tSU tH PARALLEL INPUT DATA (PDI_)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCKLO = (PCLK0+) - (PCLKO-). *PDI I5 = D15; PDI14 = D14, . . . PDI0 = D0. THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL INPUT DATA AND SERIAL OUTPUT DATA.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15*
Figure 1. Timing Diagram
Detailed Description
The MAX3891 converts 16-bit wide, 155Mbps data to 2.5Gbps serial data (Figure 2). The MAX3891 is composed of a 16-bit parallel input register, a 16-bit shift register, control and timing logic, PECL output buffers and a frequency-synthesizing PLL, consisting of a phase/frequency detector, loop filter/amplifier, voltagecontrolled oscillator, and prescaler. The PLL synthesizes an internal 2.5Gbps reference used to clock the output shift register. This clock is generated from the external 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference-clock signal (RCLK). The incoming parallel data is clocked into the MAX3891 on the rising transition of the parallel clock-input signal (PCLKI). Proper operation is ensured if the parallel-input register is latched within a window of time (t SKEW),
defined with respect to the parallel clock-output signal (PCLKO). PCLKO is the synthesized 2.488Gbps internal serial-clock signal divided by 16. The allowable PCLKO to PCLKI skew is 0ns to 4ns. This defines a timing window after the PCLKO rising edge, during which a PCLKI rising edge may occur (Figure 1).
System Loopback
The MAX3891 is designed to provide system loopback testing. The loopback outputs (SLBO) of the MAX3891 may be directly connected to the loopback inputs of a deserializer (MAX3881) for system diagnostics. To enable the SLBO outputs, apply a TTL logic-high signal to the SOS input. The same signal that controls the SOS enable input may also be used to control the SIS enable input on the MAX3881.
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5
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
PDI15 PECL 16-BIT PARALLEL INPUT REGISTER PECL PDI0 PECL
MAX3891
PDI1
BUF
SOS SLBO+
PCLKI+ PECL PCLKIPRESCALER SHIFT 16-BIT PARALLEL SHIFT REGISTER LATCH
CML
SLBO-
SDO+ PECL SDO-
RCLK+ PECL RCLK-
PHASE/FREQ DETECT
FILTER
VCO
DIVIDE BY 16 PECL
SCLKO+ PECL SCLKO-
FIL+ FIL- CLKSET
PCLKO+ PCLKO-
Figure 2. Functional Block Diagram
Applications Information
Setup and Hold Time Requirements
The setup and hold-time specifications assume that the parallel clock-input signal (PCLKI) and parallel-data input signal (PDI_) are from the same source. They should have identical common-mode voltages, signal amplitudes, and slew rates. If PCLKI and PDI_ differ significantly, the setup and hold-time requirements must be modified to account for these differences. Define tDEG as the adjustment to the setup and holdtime requirement when there are significant differences between PCLKI and PDI_. tDEG = VCMDIFF x
tT 0.6 V -V OH OL
where tT is the transition time (20%-80%) of the parallel-data and clock-input signals, VOH and VOL are the input high and low voltage, respectively, of the paralleldata and clock-input signals, and VCMDIFF is the difference in common-mode voltages of the parallel-data and clock-input signals.
6
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16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs
The adjusted setup (t SUADJ ) and hold-time (t HADJ ) requirements become tSUADJ (or tHADJ) = tSU (or tH) + tDEG
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Use controlled impedance transmission lines to interface with the MAX3891 clock and data inputs and outputs.
MAX3891
PECL Input and Output Terminations
It is important to bias the MAX3891's PECL data and clock IOs appropriately. Figures 3 and 4 show alternative PECL output termination methods. A circuit that provides 50 to (VCC - 2V) should be used in conjunction with controlled impedance transmission lines for proper termination. Use Thevenin equivalent termination when a (VCC - 2V) supply is not available. If ACcoupling is necessary, make sure that the coupling capacitor follows the 50 or Thevenin equivalent DC termination. To ensure best performance, the differential outputs (SDO and PCLKO) must have balanced loads.
Exposed Pad Package
The 64-pin exposed pad (EP) TQFP incorporates features that provide a very low thermal-resistance path for heat removal. The MAX3891 EP must be soldered directly to a ground plane with good thermal conductance.
Chip Information
TRANSISTOR COUNT: 1712 PROCESS: Bipolar
Current-Mode Logic Outputs
The system loopback outputs (SLBO) of the MAX3891 are CML compatible. The configuration of the MAX3891 current-mode logic (CML) output circuit includes internal 50 back termination to V CC (Figure 5). These outputs are intended to drive a terminated 50 transmission line.
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7
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
MAX3891
OVERHEAD GENERATION Z0 = 50 Z0 = 50 50 PECL TERMINATIONS (VCC - 2V) a. PECL TERMINATIONS V = +3.3V 130 130 50 PECL INPUTS
MAX3891
OVERHEAD GENERATION Z0 = 50 Z0 = 50 82 DC-COUPLING TO PECL OUTPUTS b. DC-COUPLING TO NON-PECL OUTPUTS +3.3V 82 0.1F 0.1F 130 AC-COUPLING TO NON-PECL OUTPUTS c. AC-COUPLING TO NON-PECL OUTPUTS 130 82 82 PECL INPUTS
MAX3891
OVERHEAD GENERATION
Z0 = 50 Z0 = 50
PECL INPUTS
Figure 3. Alternative PECL-Input Termination
8_______________________________________________________________________________________________________ _______________________________________________________________________________________
8
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
MAX3891
SCLKO+ OR SDO+ SCLKOOR SDOZ0 = 50 Z0 = 50 50 50 0.1F 0.1F HIGH IMPEDANCE INPUTS
a. PECL OUTPUT TERMINATION +3.3V 130 130
MAX3891
SCLKO+ OR SDO+ SCLKOOR SDOZ0 = 50 Z0 = 50 82 82 PECL INPUTS
b. THEVENIN-EQUIVALENT DC TERMINATION
Figure 4. Alternative PECL-Output Termination
VCC
VCC
MAX3891
50
50 SLB0+
50
50
SLB1+ SLB0ESD SRUCTURE SLB1-
MAX3881
GND OUTPUT CIRCUIT INPUT CIRCUIT
Figure 5. Current-Mode Logic _______________________________________________________________________________________ 9
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
Typical Application Circuit
155MHz REFERENCE CLOCK INPUT TERM +3.3V TERM TTL
RCLK+ RCLK- CLKSET VCC
SOS
+3.3V
TERM
PDI0
MAX3891
SDO+ TERM OVERHEAD GENERATION TERM TERM TERM TERM PDI15 PCLKI+ PCLKIPCLKI PCLKI SCLKO+ SCLKOTERM TERM SDOTERM TERM
MAX3869
FIL+
FIL-
SLBO+ SLBOTERM
0.33F
TERM
OPTIONAL CONNECTION TO MAX3881 FOR SYSTEM LOOPBACK TESTING
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50 THIS SYMBOL REPRESENTS A PECL TERMINATION WITH A THEVENIN EQUIVALENT OF 50 TO (VCC - 2V) NOTE: REFER TO APPLICATIONS INFORMATION SECTION FOR MORE ON PECL INPUT AND OUTPUT TERMINATIONS
TERM
10
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16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs
Package Information
64L, TQFP.EPS
MAX3891
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11
16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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